1. Technical Field of the Invention
The present invention relates to electronic design automation (EDA) and, more particularly, to a system and method for the automatic generation of test benches suitable for verifying integrated circuits, with particular reference to memories.
2. Description of Related Art
Exhaustive verification and testing is a major issue in the process of achieving quality custom integrated circuits and ASICs (Application Specific Integrated Circuits).
Despite the latest advances in verification technology, it is very hard and rare to obtain safe and robust ASICs which work correctly the first time they are manufactured, so that it is often necessary to review the design in several steps, each time a misbehavior is encountered.
Due the increasing complexity of ASICs and circuits in general and to the major effort required in testing and revising hardware components, exploitation of electronic design automation is today a mandatory choice.
Electronic design automation is a computer-based technology that provides designers with automated or semi-automated tools both for the designing and the verifying of custom circuit designs.
It is thus used for creating, analyzing and editing several kinds of electronic designs for the purpose of simulation, emulation, prototyping, execution or computing, and to develop further, complex systems which use a previously user-designed subsystem or component.
Typically, the end result of an EDA session is a modified and enhanced design that is an improvement over the original design, without departing from the original aim and scope of that initial design.
Since EDA is heavily based on software prototyping and simulation of integrated circuits, specific languages have been introduced to permit the specification of hardware through software. Such languages are usually referred to as Hardware Description Languages (HDL).
In fact, despite the latest advances in electronic designing which have helped significantly in reducing the design-to-product time scale, the complexity of today's ASICs is such that self-checking HDL test benches have fully replaced the simplistic vector-based methodologies used in the past.
Unfortunately, developing a self-checking test bench is a difficult and time consuming task: recent surveys show that this process can easily consume between 50% and 70% of the overall design schedule.
In other words, the so called verification problem is growing because both the design complexity and, in parallel, the required amount of stimuli required for a comprehensive circuit test, are growing.
A typical test bench development process involves a combination of preparing or purchasing models from independent suppliers, doing large amounts of HDL coding, manually gluing the pieces together and developing an exhaustive test sequence to evaluate the behavior of the ASIC in its intended environment.
Nowadays, it has become clear that even state of the art verification techniques are breaking down as ASIC complexities increase, and the trend is such that this already extremely difficult and time consuming task is getting more and more complex and critical.
Therefore, a strong need exists in the industry for a new system and method overcoming the problems of the state of the art.